IREFSTEN=0, IREFS=0, IRCLKEN=0, CLKS=00
ICS Control Register 1
IREFSTEN | Internal Reference Stop Enable 0 (0): Internal reference clock is disabled in Stop mode. 1 (1): Internal reference clock stays enabled in Stop mode if IRCLKEN is set, or if ICS is in FEI, FBI, or FBILP mode before entering Stop. |
IRCLKEN | Internal Reference Clock Enable 0 (0): ICSIRCLK is inactive. 1 (1): ICSIRCLK is active. |
IREFS | Internal Reference Select 0 (0): External reference clock is selected. 1 (1): Internal reference clock is selected. |
RDIV | Reference Divider |
CLKS | Clock Source Select 0 (00): Output of FLL is selected. 1 (01): Internal reference clock is selected. 2 (10): External reference clock is selected. 3 (11): Reserved, defaults to 00. |